The present disclosure relates to a semiconductor integrated circuit device including a standard cell with a nanowire field effect transistor (FET).
A standard cell design has been known as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell design refers to a method of designing a large-scale integrated circuit (LSI) chip by providing in advance, as standard cells, unit logic elements having particular logical functions (for example, an inverter, a latch, a flip-flop, and a full adder), laying out those standard cells on a semiconductor substrate, and connecting those standard cells together through an interconnect.
Reducing a gate length (scaling) of transistors that are a basic element of the LSI have achieved more integrated transistors, reduced an operating voltage, and improved an operating rate. However, recently, off-current has been increased due to excessive scaling, and power has been consumed more and more due to the increase in off-current, which are problems. In order to solve such problems, three-dimensional transistors having a three-dimensional structure that is changed from a conventional two-dimensional structure have been actively researched. As one technique, nanowire FETs draw attention.
An exemplary method of manufacturing a nanowire FET is disclosed in S. Bangsaruntip, et al. “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling”, Electron Devices Meeting (IEDM), 2009 IEEE International, and Isaac Laucer, et al. “Si Nanowire CMOS Fabricated with Minimal Deviation from RMG Fin FET Technology Showing Record Performance”, 2015 Symposium on VLSI Technology Digest of Technical Papers.